1. Field of the Invention
This invention relates to integrated logic circuits and more particularly to integrated logic circuits employing Schottky barrier diodes and transistors, sometimes referred to as Schottky transistor logic (STL). 2. Description of the Prior Art
The hereinabove listed publications describe the state of the prior art and the advantages of Schottky transistor logic (STL) circuits in general. STL circuits are relatively simple to fabricate in a dense integrated circuit configuration since multiple fan-out is provided by the formation of a plurality of Schottky diodes into the collector region of a transistor. Process improvements permitting the fabrication of low forward voltage drop Schottky barrier diodes (SBD's) in the order of 280 millivolts at 0.1 milliamps provides the desirable combination of high speed and lower power consumption.
A typical prior art circuit showing two cells in an STL configuration is illustrated in FIG. 1. An input signal at the input terminal (IN) either steers current away from the base of T1 or permits current drive from supply +V through base drive resistor RB1. The collector of T1 provides an output at node X which then, through one of the plurality of illustrated SBD's affects the input point of the succeeding stages such as the illustrated node Y. Base drive resistor RB2 provides base drive to transistor T2 unless the current is steered away by a down level potential at node X occasioned by transistor T1 being on. In this latter case, transistor T2 would be held off keeping node Z at an up level so that the output terminals 1-5 would not steer any current away from any further input nodes to which they in turn are connected.
A problem not addressed or solved by the known prior art arises when node X and node Y are spaced apart on an integrated circuit chip giving rise to a metallurgy resistance in the order of 12 ohms to 120 ohms or even more. This is significant when compared with the value of base drive resistance for the resistors RB1 and RB2 which are usually in the order of 2,000 - 8,000 ohms. In the case where transistor T1 is on, the voltage drop between node Y and ground potential must include not only the diode drop of the Schottky barrier diode and the voltage drop through transistor T1 but further take into consideration the metallurgy resistance, these last three mentioned elements forming a voltage divider with base drive resistor RB2 at node Y. This results in a relatively high down level at receiving nodes such as node Y, degrading the noise tolerance of the overall logic network.